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: The MOSFET

INTRODUCTION

The number of internet users in 2020 is approaching the 5 billion mark. Each of these users possesses a personal computer (PC) with which he or she communicates with the rest of the world. At the same time, big computers in organizations around the world help solve complex problems like predicting the local weather. In universities, the computer is an everyday tool for both teaching and research. Furthermore, mobile or cellular communication would not exist had it not been for the availability of computing power inside the phone itself and at the installations of every major phone company around the world. At the heart of these technologies (and many more) lies the metal-oxide-semiconductor field effect transistor, MOSFET for short—an electronic switch.

PRINCIPLE OF OPERATION OF THE MOSFET

A diagram of a MOSFET is shown in figure 7.1a. A P-type (or N-type) Si substrate) has three metal contacts on top of it. The ones to the left and right are called source and drain respectively and are labelled S and D. Below each of the two there is a heavily doped N region (usually symbolized N++ or n++) which forms a PN junction with the Si substrate. The third contact, the gate, abbreviated as G in Figure 7.1a, is not in contact with the Si substrate but a thin layer of insulating oxide has been grown between the gate electrode and the Si substrate. This oxide was Si02 from the invention of the MOSFET until only a few years ago. It has now been replaced by Hf02(hafnium dioxide) for the very short-channel MOSFETs now in operation. For the sake of simplicity, we will continue to use the term oxide to include both Si02 and Hf02.

Assume for a moment that no voltage is applied to the gate while a positive voltage VDS is applied between source and drain. The potential energy diagram, i.e. the change of the conduction band minimum as a function of the distance x along the channel, is shown in figure 7.1b. The steps in the potential energy under the source and drain areas are due to the built-in barriers of the PN junction in the respective areas. Electrons from the source electrode cannot flow to the drain electrode because of the barrier that has been formed, so the current IDS is therefore nearly zero. This barrier can be reduced and current Ids may

a Layout of a MOSFET

FIGURE 7.1a Layout of a MOSFET.

flow if a positive voltage, Vcs> with respect to the substrate is applied to the gate. If substantial current is to flow this voltage must exceed a certain threshold voltage V,/,, to be calculated later, i.e. we must have Vcs > Vth- We have already seen such a situation in connection with the vacuum transistor, but what happens in MOSFETs is much more complicated and demands greater analysis.

b,c Variation of the conduction band minimum E along the distance from source to drain given a gate voltage V which is (a) less than the threshold voltage and (b) larger than the threshold voltage

FIGURE 7.1 b,c Variation of the conduction band minimum Ec along the distance from source to drain given a gate voltage VG which is (a) less than the threshold voltage and (b) larger than the threshold voltage.

d Formation of the channel connecting the source to the drain

FIGURE 7.1 d Formation of the channel connecting the source to the drain.

When Vgs < VJ/,, this voltage will push away from the oxide-Si interface the holes, i.e. the majority carriers of the P semiconductor. As the holes move away from the interface, they expose the negative charge of the acceptors and hence create a negative depletion region in the Si semiconductor immediately below the oxide, see figure 7.2a. Upon further increase of the gate voltage such that Vgs > VJ* not only the holes have been pushed away from the oxide/Si interface, but also the electrons, the minority carriers, have been attracted to the interface and have concentrated there, see figure 7.2b. The net effect is that a thin layer in the Si semiconductor, adjacent to the oxide, has changed its character from P-type to N-type and thus a channel of N-type connects the source to the drain and current IDS can flow. This amounts to lowering the barrier as shown in figure 7.1c. The channel is shown schematically in figure 7.1d. We note that in most applications the substrate is short-circuited with the source, so the subscript S in Vgs may refer also to the source. Henceforth, therefore we may occasionally omit the second subscript S in Vgs, Vds or Ids- The value of the gate voltage VGs required to achieve inversion of the semiconductor under the gate is what we have called V,h.

The two types of changes in the semi-conductor below the gate when the MOSFET is (a) below threshold and (b) above threshold

FIGURE 7.2 The two types of changes in the semi-conductor below the gate when the MOSFET is (a) below threshold and (b) above threshold.

a The band structure of a metal, an oxide, and a semiconductor when they are isolated from each other

FIGURE 7.3a The band structure of a metal, an oxide, and a semiconductor when they are isolated from each other.

We must now look in more detail at the band diagrams of this structure. Figure 7.3a shows the band diagrams of the components of a MOSFET when isolated from each other. Epm and W,„ stand for the Fermi level and workfunction in the metal, while Eps and Ws are the corresponding quantities in the semiconductor. The remaining symbols have their conventional meaning. When the three material components are connected to form a MOSFET (we emphasize that this is only, as before, a thought experiment), the Fermi levels of all the component materials will equalize just as in the PN and Schottky junctions that we discussed in chapter 3. The resulting band structure is shown in figure 7.3b. The width of the oxide is denoted by d. For the Fermi levels in the metal and semiconductor to equalize, an exchange of charge must take place between them, so a surface layer of positive charge appears on the metal and a negative layer on the semiconductor. Just as in the Schottky diode, this exchange of charge will create a band bending in the semiconductor which will be equal to cpms = Ep„, - Eps = Wm-Ws, as shown in figure 7.3b.

When a positive voltage is applied to the gate, see figure 7.3c, the initial bending downwards that was caused by ms increases even more and the bottom of the conduction Ec of P-Si at the Si02/Si interface approaches the common Fermi level whereas the top of the valence Ev of P-Si moves away from the Fermi level. This picture corresponds to the physical process of the movement of holes away from the Si02/Si interface. The movement of both Ec and Ev of Si with respect to Eps locally, guarantee that the electron concentration is increased and that of holes is decreased.

As the voltage Vds is further increased there comes a point where the bottom of the conduction band Ec of Si comes very close to the Fermi level, in which case electrons fill

b,c The band structure of a p-MOSFET when the three constituents of figure 7.3a are in contact

FIGURE 7.3b,c The band structure of a p-MOSFET when the three constituents of figure 7.3a are in contact: (b) no gate voltage VG> (c) a small VG>0.

the conduction band of Si substantially while holes are depleted even more, see figure 7.3d, thereby establishing locally the condition n> p which amounts to what we have called inversion. The variation of the various charges as VGS is changed, is shown in figure 7.4. In figure 7.4a, we show the charges present in a MOSFET when 0 < Vcs < Vlh, where Vlh is the critical value of Vcs when inversion has just occurred. A more precise definition and calculation ofV will be given immediately below. Qm stands for the positive charge per unit area of the surface layer of the gate metal at the metal/S/02 interface, Q„ stands for the charge per unit area of the electrons in the conduction band of Si and Qa stands for the charge per unit area of the depletion region which is due to the exposed (not compensated by holes)

d,e The band structure of a p-MOSFET when the three constituents of figure 7.3a are in contact

FIGURE 7.3d,e The band structure of a p-MOSFET when the three constituents of figure 7.3a are in contact: (d) VG>Vth and (e) VG<0.

charge of the acceptor ions. If / is the width of the depletion region and assuming a fully depleted region we have Од = —eNAl.

The situation when Vgs > Vth is shown in figure 7.4b. It can be seen that Q„ has increased abruptly and significantly due to the exponential nature of the Fermi-Dirac probability distribution, whereas QA has increased only marginally. It must be noted that beyond the onset of inversion the width of the depletion does not increase anymore because the essentially planar charge Q„ screens the applied electric field and prevents it from penetrating any further into the Si semiconductor space charge layer. Its width l then attains a maximum value lmax. What happens if Vgs <0? That situation is simpler. The bands bend upwards, Ey of Si comes closer to the Fermi level, and the concentration of holes near the interface of Si02 / Si increases as a result of the physical process of the attraction of holes by the now-negative VGS. The band picture is shown in figure 7.3e and the charges

Charges in the MOSFET structure as V is varied

FIGURE 7.4 Charges in the MOSFET structure as VG is varied: (a) 0 < Vgs < V^,, (b) Vcs > V^, and (c) ^gs < 0.

in figure 7.4c. Qs in figure 7.4c stands for the surface charge of holes on the semiconductor side of the interface.

A more quantitative definition of V#,, the value of the gate voltage at which inversion has just occurred, can be given as follows. In figure 7.5a, we show the position of the Fermi level of a P-type semiconductor. Generally speaking, for a P-type semiconductor to transform into a N-type semiconductor with the same number of electrons as the number of holes it had originally, the Fermi level Epp must move up the band gap by 2-(£r — Epp), with

a The energy interval by which the Fermi level of a P-semiconductor has to be lifted to transform it to an N-semiconductor

FIGURE 7.5a The energy interval by which the Fermi level of a P-semiconductor has to be lifted to transform it to an N-semiconductor.

being the Fermi level of an intrinsic semiconductor (located approximately at mid-gap). The transformation may be accomplished by, say, extra doping. In the case of a MOSFET, the inversion from P-type to N-type is not accomplished by doping but by band-bending, so the bottom of the conduction band Ec must bend by Vs = 2-(£r — Epp) = 2-vPb. This is the required voltage drop in Si for inversion. This band bending takes place mainly near the Si / Si02 interface and quickly goes to zero in the bulk of Si. This is shown in figure 7.5b. Essentially this has already been shown in figures 7.3d but without any further definitions. Assuming complete depletion of carriers in the band bending region, i.e. assuming p = -еМд, we get from the one-dimensional Poisson equation in the manner we have done for the Schottky diode

where z is the direction along the depth of the MOSFET and with esi the dielectric constant of Si.

b The variation of the potential along the depth of the Si layer in a MOSFET

FIGURE 7.5b The variation of the potential along the depth of the Si layer in a MOSFET.

But the gate voltage Vcs is applied on the metal electrode. Hence a certain proportion of it is droped in the oxide. Taking into account that there is already a band bending present (equal to Oms) at Vcs = 0 we have for V,h

The difference in workfunctions Oms between the metal and the semiconductor has an algebraic sign which is negative if the conduction band bends downwards and positive if it bends upwards. From equation 2.63 we have (substituting p = NA for a P-type semiconductor)

On the other hand, treating the charges on either side of the oxide as a capacitor we have

where Cox = eox/d, d is the thickness of the oxide and eox is the dielectric constant of the oxide.

In equation 7.4 we have assumed that just prior to inversion Q„ can be neglected. Note also that Qa,Q,i denote charges per unit area and consequently Cox denotes the oxide capacitance per unit area. Note also that the width of the depletion region in Si has attained its maximum value. What is this maximum value? The value that corresponds to a band-bending of 2*Рg. Using the theory of PN junction (see equation 3.45) we have that

so that equation 7.2 becomes

Equation 7.4 should be viewed as an approximation for the voltage drop in Si02 because it has been assumed that the oxide is free of trapped charges inside it and of charged interfacial defects in the Si02 / Si interface. However, equation 7.2 remains exact if the voltage differences produced by such charges are included in Д Vox-. It is worthwhile pointing out that if a capacitance measurement is made as Vcs is increased, a negative step will be observed

(a) Typical I-V characteristics for constant V and (b) I-V characteristic for constant V

FIGURE 7.6 (a) Typical ID-VD characteristics for constant VG and (b) ID-VG characteristic for constant VD.

at VGS = Vth. This happens because the capacitance of the MOS structure C before threshold is Cox, whereas after threshold it is given by

where Cd is the capacitance of the depletion region, see figure 7.4a-c to see why this is so. The step becomes positive if the substrate is N type.

We now examine qualitatively the dependence of the current Ids on the voltage VDS between source and drain. Assuming a gate voltage such that VGS > Vn„ i.e. that the N-type channel has been created, an increase in Vos initially produces a corresponding linear increase in Ids, see figure 7.6a where the complete characteristics are given. This is easily understood; the electrons flow with a higher drift velocity in the channel. The device acts as a resistor. As VD5 is further increased, we observe that the rate of increase slows down and the current eventually almost saturates at VDs = Vj>s1.

What physically happens is that as Vos increases, the PN junction below the drain becomes more negatively biased and hence its depletion region widens. It initially decreases

Cross-section of the MOSFET channel (a) below and (b) above saturation voltage. The dotted lines denote the extent of the depletion regions

FIGURE 7.7 Cross-section of the MOSFET channel (a) below and (b) above saturation voltage. The dotted lines denote the extent of the depletion regions.

the depth of the channel, see figure 7.7a, slowing down the rate of increase of the current, and finally “pinching” the channel. This happens just below the drain. Further increase of VDS beyond Vos1 moves the “pinching” point towards the source and effectively decreases the length of the channel, see figure 7.7b. A further, very small increase in the current is then observed. The variation of Ids with Vgs is given in figure 7.6b. This is easily understood. Below threshold there is no current while above it a higher gate voltage attracts more electrons in the channel and the current increases accordingly. The reader should have revolted by now. If part of the channel is deprived of its carriers (since the channel has been pinched), how come the current remains constant and not drop? We will delve into this matter later but the short answer is that a channel of a very small cross-section survives that can carry the current under the action of very high electric fields inside the “pinched” region of the channel.

 
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