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We have seen in this chapter that Si MOSFETs suffer from short channel effects, the lowering of the Vo, with channel length L for a given L, and the drain induced barrier lowering effect, the dependence of V,;, on drain voltage. Both effects degrade the performance of the transistor. Common to both cases is the loss of control of the channel by the gate. With the planar structure that we have considered so far there is not much that one can do given the replacement of Si02 by Hf02. A way forward from this problem is to increase the number of gates that surround a channel as shown in figure 724. By etching Si, a Si fin is produced which is then surrounded by a dielectric first and then by a metal, thus producing a tri-gate FET. Actually, the FinFET as it is called is more of a double-gate FET than a tri-gate FET for the following reason: the top gate does not have a significant area when compared to the other two gates, and hence this gate is less effective.

The equations governing transport in the FinFET within the classical description (which includes the Schroedinger equation) are no different than the ones we have already presented [7]. They have to be solved of course in three dimensions and that can only be performed numerically and with greater difficulty than for the conventional MOSFETs. However, within the approach of a FinFET as a double-gate FET there are what are called compact models, models that perform some initial approximations so that a fast solution is

A Fin-FET in three-dimensions. The gate surrounds the channel from three sides

FIGURE 7.24 A Fin-FET in three-dimensions. The gate surrounds the channel from three sides.

obtained. Such compact models may assume that the acceptor doping is low [8] or assume other simplifications. The reader should have little difficulty in following these compact models given the information presented so far in this book. The increased performance of FinFETs is shown in the following figure 7.25, which portrays the difference in leakage currents (figure 7.25a) and gate delays (figure 7.25b) between the conventional planar geometry and the fin geometry of Si MOSFETs.

Superior performance of the Fin-FET compared to the planar one

FIGURE 7.25 Superior performance of the Fin-FET compared to the planar one: both (a) the subthreshold current and (b) the gate delay are smaller for the Fin-FET.


7.1 Show that the capacitance of a MOS structure is

where the above symbols have the same meaning as in the text. Justify any intermediate formula you may use.

7.2 Prove the following relation at VDS=0 between the gate voltage VGS and the capacitance C of the MOS structure

where the above symbols have the same meaning as in the text.

  • 7.3 The transconductance gm of the MOSFET was derived in the text on the assumption that the DC derivatives can be used in place of the AC derivatives. Assume that the time dependent current Ids in the saturation regime can be found by substituting VGS+ugs for VGS in equation 7.16. How is this gm different from the one given in the text?
  • 7.4 (Contact Resistance-Tunnel Current) Use the theory of tunnelling developed in chapter 6 to calculate the tunnelling current between the metal contact and the heavily doped source in reverse bias. Initially use a linear approximation for the barrier. Ignore the image potential.
  • 7.5 Calculate the tunnelling current using the full potential of equation 3.75.


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  • 3. A. Pirovano, A.L. Lacaita, and A. Spinelli. IEEE Trans. Electr. Dev. 49, 25(2002)
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  • 7. J.P. Colinge, J.C. Alderman, W. Xiong, and C. Rinn Cleavelin. IEEE Trans. Electr. Dev. 53, 1131(2006)
  • 8. A. Tsormpatsoglou, C.A. Dimitriadis, R. Clerc, G. Panakakis, and G.Ghibaudo. IEEE Trans. Electr. Dev. 55, 2623(2008)
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