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The Organisation of a computer system can be conceived in terms of a series of levels or abstraction maintaining a level hierarchy in which each level in the hierarchy with more or less fixed tasks and responsibilities performs a specified range of operations at minimum cost, and relies on its just upper level in the hierarchy. All machine activities are usually obtained by means of the operations carried out by three basic levels, namely the processor level, the register level, and - the lowest one - the gate level. The type of components to be used in each such level is mostly standardized, but each of these three levels can be realized in many different ways that entirely depend on the specific Organisation being followed in building up a computer system. Processor-level system is absolutely well defined, and comprises CPUs and other processors, memories, I/O devices, and interconnection networks. Its performance is measured and evaluated by a non-profit Organisation named System Performance Evaluation Corporation, often abbreviated as SPEC. Register level consists of combinational devices (such as multiplexers, decoders, adders, and word gates), sequential devices (such as registers, counters etc.), and various general-purpose programmable elements (including PALs, PLAs, FPGAs, and ROM). The gate level is the lowest level in the architectural design of computing systems. This level comprises logic gates as basic functional components that operate on a well-defined theory based on Boolean algebra. Unlike combinational circuits, sequential circuits have memory, which is usually built from gates, and 1-bit storage elements (flip-flops) that store the circuit's state and are synchronized by means of clock signals.
a. How many selection inputs are there in each multiplexer?
b. How many multiplexers are there in the bus?
c. What size of multiplexers is needed?
[Hint: b) Each multiplexer transfers one bit of the selected register. The number of multiplexers needed to construct the bus is equal to n, the number of bits in each register. Here, it is 32.
c. The size of each multiplexer must be к x 1, where к is the number of the registers, since it multiplexes к data lines, each from a register.
Suggested References and Websites
Armstrong, J. R. and Gray, F. G. Structured Logic Design with VHDL. Englewood Cliffs, NJ: Prentice- Hall, 1993.
Hamacher, C., Vranesic, Z. G., and Zanky, S. G. Computer Organisation, 5th ed. New York: McGraw- Hill, 2002.
Langholz, G., Francioni, J., and Kandel, A. Elements of Computer Organisation. Englewood Cliffs, NJ: Prentice-Hall, 1989.
Mano, M. Logic and Computer Design Fundamentals. Upper Saddle River, NJ: Prentice-Hall, 2004.
Siewiorek, D. P, Bell, C. G., and Newell, A. Computer Structures: Reading and Examples. New York: McGraw-Hill, 1982.
Tanenbaum, A. S. Structured Computer Organisation, 4th ed. Upper Saddle River, NJ: Prentice-Hall, 1999.
System Performance Evaluation Corporation: web page: www.spec.org.
Standard benchmarks are used to measure and compare the performance of different computer systems.