Desktop version

Home arrow Computer Science

  • Increase font
  • Decrease font


<<   CONTENTS   >>

Control and Status Registers

There are various types of CPU registers available in most machines, used exclusively by the CPU to control its own operation. On a majority of machines, most of these registers are not accessible to the user, a few of them on some machines are found to be user-visible (program counter [PC] in DEC VAX system), and at certain points in time, some of them are visible to the machine instructions when executed under supervisor mode. However, there are four key registers in the processor that are essentially attached to instruction execution, which are described below.

Program Counter (PC): To execute a program, the CPU always keeps track of the address of the current instruction in successive memory location to be fetched, using a register known as the program counter (PC). After fetching the current instruction using the content of PC, the PC value is then automatically updated to point to the next instruction to be fetched in sequence until a branch or a jump instruction is encountered. The presence of a branch instruction in any form may modify the contents of the PC and may load a different value.

Instruction register (IR): The contents of the memory location being pointed to by the PC are then fetched by the control unit of the CPU. The contents of this memory location if interpreted as an instruction to be executed are loaded into the IR. Symbolically, this can be written as IR <- [[PC]].

Memory address register (MAR): This register contains the address of a memory location the contents of which are to be fetched.

Memory buffer register (MBR): This register contains the word most recently read from memory or a word to be written to memory.

Besides, there are a number of other registers found in particular CPU designs that are used to contain control and status information. They are often known as the program status word (PSW) or program control block (PCB) and contain condition codes and other status information.

During execution, the instruction being pointed to by the PC is fetched and is loaded into the IR where it is decoded. Data is exchanged with memory using the MAR and MBR. User-accessible registers often exchange data with the MBR. In a bus-organised computer, the MAR is directly connected with the address bus and the MBR is directly connected with the data bus. Within the CPU, the ALU may have access to the MBR and other user-accessible registers, or alternatively, there may be additional buffering facilities at the boundary of ALU, serving as input and output registers (INPR/OUTR) for the ALU. These registers involve in the exchange of data with MBR and other user-accessible registers.

Last but not least, there is an issue related to register length that often made an impact on CPU design. Registers that are used to hold addresses must be long enough so that they can hold the largest address. Data registers also should be capable of holding values of most data types. Some machines exploit two contiguous registers to be used as one for holding double-length values (double precision), and also four contiguous registers to be used as one for holding extended length values (extended precision). However, not all registers are found in all the CPUs. Even the size of the registers is different in different machines. Also, the number of registers to be employed is not the same in all the CPUs. All these and similar aspects are entirely a designer's choice, depending on trade-off and other factors, including the operating system to be used and the ultimate objectives to be attained.

The processors of a somewhat different class of architecture, known as RISC architecture (explained in Chapter 9), have the abundant number of registers, and most of the instructions in the instruction set of those processors are thus register-oriented. Moreover, the number of registers and their internal organisation in this type of processors introduced by different manufacturers are also found varying over a wide range.

In fact, the increasing number of registers and their availability in various types in the processors, the growing number of functions they are to perform, and of course, their more efficient internal organisation actually set the stage for constantly improving processor performance.

Register Organisation in Microprocessor: IA-32/64 and MC68000

Most contemporary CPUs are realized today by the modern versions of powerful, versatile single-chip processors or microprocessors introduced by different vendors. But the two leading representative microprocessors in the industry are Intel X-86 series from Intel and MC 68000 series from Motorola with their constantly released new members, such as 8- 16-, 32-, and 64-bit microprocessors in their own families. The register organisation of the microprocessors that came from these two families can be thus cited here as an example to give an overall idea as to how the register organisations are actually planned in microprocessor implementations, in general.

Motorola MC68000 Series

Although the initial product of the MC68000 series was essentially a hybrid between 16- and 32-bit architectures, subsequent releases were truly in 32-bit architecture. The 32-bit register set is partitioned into eight data registers and nine address registers, including one stack pointer (SP) register. There is also a 32-bit PC and a 16-bit status register (SR). The data registers although primarily used for data manipulation are also used for addressing similar to index registers, thus giving rise to a flavour of general-purpose activities. The 8- 16-, and 32-bit-width data operations are allowed in these registers, which are determined by the respective operation codes given in the instruction. The address registers contain 32-bit addresses; two of these registers are also used as SPs, one for users and the other for the operating system, depending on the current execution mode. Both these registers are numbered A7, because only one will be used at a time. There are, however, no special- purpose registers.

The instruction set used in Motorola processor is a reasonably regular one. The available registers are, however, divided into two functional components, thereby enabling the processor to save one bit on each register specification that consequently helps to make the code somewhat shorter in length and more efficient. This approach appears to be an effective compromise between complete generality and code compaction.

Intel IA-32 Architecture

The Intel X-86 uses a different approach in its register organisation, which is relatively tricky. Every register here is special-purpose, although some registers are also used as general-purpose or multipurpose. The multipurpose registers hold various data sizes {bytes, words, or double word) and are used for almost any purpose, as dictated by a program. The earlier 8086, 8088, and 80286 contain 16-bit architectures having a set of registers, which are also now a subset of registers provided in the full 32-bit internal architectures of 80386 to Core-2 microprocessors for maintaining downward compatibility with the earlier versions (Brey Barry B.). The register organisation of the member processors under IA-32 includes eight 32-bit general-purpose registers, such as EAX EBX, etc. used for all types of X-86 instructions, including indirect addressing. Some of these registers can also be used for other special purposes; i.e. the registers ECX, EDI, and ESI are implicit in the string instructions. The processor also has six 16-bit segment registers, including CS, SS, DS, ES, FS, and GS that contain segment selectors to identify specific segments containing instruction to be executed, the user-visible stack, and segments with other information for dedicated and implicit usages. Although this arrangement provides the benefit of compact encoding, it comes at the cost of reduced flexibility. Moreover, IA-32 provides a 32-bit register called EIP that contains the address of the current instruction (i.e. our usual PC), and a 32-bit register called EFLAGS that contains numerous condition codes, and control bits, such as sign, overflow, carry, and trap flag (TF), interrupt enable flag (IF), as well as various mode bits indicating the state of the processor. In addition, there exist other registers, such as numeric, control, status, and tag word, especially committed to the floating-point unit. Apart from all these, IA-32 employs four control registers (register CRO through CR3) and a total of eight 64-bit MMX registers. In fact, the processor does not include specific MMX registers. Rather, the processor uses an aliasing technique that enables the eight existing floating-point registers (each of 80 bits, out of which 64 bits are used for mantissa and the rest 16 bits for exponent) to be used to work as an MMX register to store MMX operands only in the 64-bit mantissa portion of these registers. Thus, these eight registers actually serve a dual purpose. When used by an MMX instruction, these registers are referred to as MM0 through MM7. To provide parallel operation (SIMD (single-instruction multiple data) approach, see Chapter 10) on standard multiple data lengths, four new packed data types are defined in MMX. These are explained in Section 3.9 (MMX data types) and Section 3.10.8.1 (MMX operations).

In order to access and specify the global and local descriptor tables located in the memory system (see Chapter 4), IA-32 contains a few registers that are not directly addressable by the software, known as program-invisible registers. Two such registers are GDTR (global descriptor table register) and IDTR (interrupt descriptor table register), which contain the base address of the descriptor table and its limit. One of the global descriptors is set up to address the local descriptor table which is accessed by the LDTR (local descriptor table register).

Intel IA-64 Architecture

The register organisation of the member processors under IA-64 contains many useful features, including most of the features of register organisation of IA-32, and some other types of registers of its own. However, we restrict ourselves at this point from entering into any further details on it. In fact, IA-64 (Core 2, Pentium 4, and onwards) provides sixteen 64-bit general-purpose registers, such as RAX RBX etc., including eight additional 64-bit registers (R8 through R15) used for all types of X-86 instructions. These additional registers are addressed as a byte, word (16 bits), doubleword (32 bits), or quadword (64 bits), but only the rightmost 8 bits is a byte. In addition, IA-64 provides a 64-bit register called RIP that contains the address of the current instruction (i.e. our usual PC), and also a 64-bit register called RFLAGS consisting of a set of 1-bit status and control flags that contains numerous condition codes and various mode bits indicating the state of the microprocessor, thereby controlling its operation. In the current architectural design and definition, the upper 32 bits of RFLAGS remain unused (Dulong, C).

A brief detail of the register organisations with figures of both Motorola 68000 series and Intel IA-32 and IA-64 processors is given in the website: http://routledge. com/9780367255732.

 
<<   CONTENTS   >>

Related topics