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Static RAM (SRAM)

A static RAM (SRAM) consists of circuits using the same logic components that are used in the processor, and is capable of retaining their state as long as power is applied. Traditional flip-flops are used to realize this memory that stores the binary information following conventional logic-gate configurations. Each static cell can store a single bit of either 0 or 1. Each cell generally requires six transistors for its realization using both bipolar and MOS technology.

Figure 4.3 schematically illustrates how a static RAM (SRAM) cell can be implemented. Two inverters are cross-connected to form a latch. The latch is connected to two bit lines of transistors and T2. These transistors actually act as switches that can be opened or closed under control of word line. When the word line is at the ground level, the transistors are turned off, and the latch retains its state. For example, let us assume that the cell is in state 1, if the logic value at point Q is 1 and at point C2 is 0. This state is maintained as long as the signal on the word line is at the ground level. The static RAM cell, however, can be realized using CMOS cell following the line as shown in Figure 4.3. The power supply voltage required for modern low-voltage versions of CMOS SRAMs is 3.3V, while it was 5V in older versions. SRAMs are said to be volatile memories since their contents are lost when power is not present.

Read Operation: For reading the state of the SRAM cell, the word line is activated by closing switches T, and T2. If the cell is in state 1, the signal on bit line b is high and the signal on bit line b' is low. The opposite is true when the cell is in state 0. Thus, b and b' are complements of each other. Read/Write logic circuits attached at the end of the bit lines are used to monitor the state of b and b' and accordingly set the output.

FIGURE 4.3

A static RAM cell.

Write Operation: For write operation, the state of the cell needs to be set, and this is done by placing the appropriate value on bit line b and its complements on b', and then activating the word line. This consequently forces the cell into the corresponding state. The signals required on the bit lines are generated by the Read/Write logic circuits.

Two distinct advantages of CMOS SRAMs are observed. Firstly, they can operate with very low power consumption. Secondly, these SRAMs can be accessed very quickly. Access times are of just the order of a few nanoseconds as reported in commercially available chips. That is why, SRAMs are found to be extremely suitable for use in systems devoted to time-critical applications (e.g. real-time systems) where speed of execution is a major concern.

The RAM chips 6116, 6164 (or 6264), and 61256 (or 62256) are static RAMs and all are of CMOS type. These IC chips are run by single power supply +5V. The access time of these chips, on average, varies in the range of 100-120 ns. The outputs are tri-stated and TTL compatible. Although these memories are called CMOS RAMs, the memory cells use NMOS technology,and CMOS technology is used for the fabrication of the decoding, control, and internal interface circuits. Full CMOS RAMs are, however, also available for low-power applications.

The details of the realization of CMOS cell with figure are shown in the web site: http:// routledge.com/9780367255732.

Dynamic RAM (DRAM)

Static RAMs are, no doubt, operationally fast, but they are realized at high cost and consume more space because several (six transistors) transistors are required to construct each cell. Designers were thus desperately looking for suitable methodology that could make less expensive RAMs using relatively simpler cells. Appropriate methods were ultimately found out to construct such simpler cells. Incidentally, such cells are inherently unable to retain their state indefinitely, rather have a tendency to change their own state dynamically, even when the power is on. Due to this attribute, the cell is commonly referred to as Dynamic RAMs or DRAMs [Jacob, В].

A dynamic RAM is made with cells that store data as charge on capacitors. The presence or absence of a specified amount of charge in a capacitor is interpreted as a binary 1 or 0. This capacitor is controlled by a transistor-switching circuit. Because capacitors have a natural tendency to discharge, the charge stored in a dynamic RAM cell tends to leak away with time, even with power constantly applied. Consequently, the information stored in it is thus in the way of being lost. Since the cell is usually required to store information for a much longer time, the amount of charge content lost from the cell by this time must be then periodically compensated (recharged) properly by restoring the capacitor charge to its original value. This process of restoration of charge in condenser must be carried out within a time duration before the charge of the capacitor decays to a level which is the minimum threshold for logic 1. This restoring process is known as refreshing the DRAM. Dynamic RAM thus requires periodic charge-refreshing mechanisms to maintain its stored data intact. As long as the charge in the capacitor stays above the threshold, no data is lost. Otherwise, if the capacitor is allowed to discharge too much and consequently the charge goes below the minimum threshold, logic 1 will eventually move to logic 0, thereby causing severe damage to the stored information. Most of the commercial DRAMs thus require refreshing the capacitor within a 2-4 ms interval.

It has been observed that about 3 % of the memory usage time only is spent on refreshing, and hence, refreshing has very little impact on the performance of the memory. It should be noted that while refreshing is going on, normal memory access cannot be performed. However, refresh cycles and normal memory access cycles can be interleaved and it has been accomplished in the advanced IC chip design.

A typical DRAM cell structure for an individual cell that stores one bit of information is depicted in Figure 4.4. The cell is constructed simply by a capacitor C and a transistor T. The transistor T here acts as a switch which is closed (allowing current to flow) if a voltage is applied to activate the address line and is open (no current flows) if no voltage is present on the address line. The address line is activated only when the bit value from this cell is to be read or written.

FIGURE 4.4

A scheme of typical DRAM memory cell structure.

Write Operation: For the write operation (i.e. to store information) in the cell, a voltage either high representing 1 or low representing 0 (i.e. an appropriate voltage signal) is applied to the bit line. A signal is then applied to the address line to turn the transistor T on. This causes a known amount of charge (bit value) to be transferred to the capacitor C to store. Charge is transferred to the capacitor C only if the data line is in the 1 state, and no charge is transferred, if the data line is in the 0 state.

Read Operation: For the read operation, the address line for the targeted cell is selected and then activated. As a result, the transistor T is turned on, and the charge already stored, if any, in the capacitor is transferred, and is fed out onto a bit line, and then to a sense amplifier for detection. The sense amplifier compares the capacitor voltage to a reference value (threshold value) that determines whether the cell contains logic 1 or logic 0. The readout from the cell is destructive in nature (DRO) that discharges the capacitor C. This occurs because the selected storage capacitor C comes in parallel with the stray capacitor C, of the bit line. Usually, the value of Q is much larger than C because many such cells are connected to the same column line. Thus, the information being readout is now amplified and subsequently restored (rewritten again into the cell) in C for future use. This operation may, however, be combined with the periodic refreshing operations as required by dynamic memories of this type. The read operation now comes to an end. With its usual access circuitry, this memory cell also requires a few additional arrangements for keeping the provision of:

  • • Suitable mechanism for refreshing
  • • Necessary arrangement to recover the cell status due to destructive readout.
  • • DRAM is often bit-organised. Therefore, the read/write operation can be done for one bit at a time, and for this reason, a DRAM with a large capacity requires comparatively more address lines than its counterpart a Static RAM.

Still the distinct advantages of this memory cell are:

  • • Low cost per bit.
  • • Its small size which, in turn, makes the IC chip small in size with high cell (bit) density. This is possible due to the simplicity in realization of the DRAM cell.
  • • Smaller in size leads to high portability.
  • • Having low power consumption reduces the running overhead as well as less heat generation, thus, requiring less air-conditioning to keep it properly operative.

Since a DRAM with a large capacity requires more address lines; for example, a 4 Mb x 1 DRAM requires 22 address lines (4 Mb = 222). But, to save pins, address multiplexing is used to specify the address of each cell. The same pins of the IC package are thus multiplexed to input both the row address as well as the column address of a cell. Hence, appropriate decoders are required for this purpose. To load these two addresses into the row decoder and column decoder, two strobe signals RAS'(= Row Address Select) and CAS'(=Column Address Select) are used externally.

CMOS semiconductor cell is found in common use for main memory (primary memory) in almost all commercial computer systems of today. However, the detailed implementation of the sense amplifier and refreshing mechanism associated with its implementation are beyond the scope of this discussion.

Schemes For Refreshing DRAM

Normal decay of stored charge from the capacitor creates problems only when the information is read from the cell, because writing on the cell means putting some amount of charge to store in the capacitor. Thus, refreshing is mainly required to restore the charge level to its original value before any such reading is carried out. Refreshing is periodically done by cycling through the words once every 2-4 ms to restore the charge already decayed. This requires an extra control circuitry for refreshing mechanisms that are to be interleaved with normal memory access operations. Naturally, realization of dynamic RAM requires somewhat extra circuitry and additional mechanisms than those of their static counterparts. However, there are several types of refresh operations. Those are, namely:

i. RAS' Only Refresh

ii. CAS' Before RAS' Refresh

iii. Distributed Refreshing

iv. Hidden Refresh

v. Burst Refresh

A brief detail of different types of refresh operations is given in the following web site: http://routledge.com/9780367255732.

 
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