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Exercises

  • 4.1 What is meant by memory hierarchy? Why is such an hierarchy required? What is the basis on which such an hierarchy pyramid had been developed? Draw a suitable memory hierarchy block diagram with the parameters you have considered.
  • 4.2 Discuss big-endian and little-endian methods used in byte ordering. What is the difference between direct access and random access?
  • 4.3 Discuss the parameters that determine the performance of a memory system.
  • 4.4 Describe with a suitable diagram the storage structure of a bipolar storage cell and explain the reading and writing operations on the cell.
  • 4.5 Explain with a diagram the reading and writing operations of a basic static MOS cell.
  • 4.6 "In spite of requiring additional arrangement for its operation, memory system realized using DRAM cell is still more advantageous than its counterpart SRAM cell". Justify the statement with your comment.
  • 4.7 Why does a DRAM cell need refreshing? State briefly the different schemes being used for refreshing DRAM.
  • 4.8 How manyl28 x 16 RAM chips are needed to construct a memory capacity of 4,096 words (16 bit word)? How many lines of the address bus must be used to access a memory of 4,096 words. How many of these lines will be common to all chips? For chip select, how many lines must be decoded?
  • 4.9 Using four numbers of 128 x 8 RAM modules, design the following memory organisations: (i) 512 x 8, (ii) 256 x 16, (iii) 128 x 32
  • 4.10 Describe with diagram the two-dimensional (2D or 2'/®) organisation of semiconductor memories. Show with a diagram one such representative IC chip.
  • 4.11 What is the difference between SDRAM and DRAM? What are the different types of ROM? Discuss their merits and drawbacks.
  • 4.12 Describe the technique being used in erasing EPROM. What are the drawbacks of this method?
  • 4.13 What is virtual memory? Why is it called so? What are the advantages obtained from a virtual memory system?
  • 4.14 What is meant by logical address space and physical address space? Explain the mechanism with an example how logical address is converted into physical address (address translation mechanism)?
  • 4.15 It is observed that with the advent of more advanced technology, the chip can be developed with increasing capacity of memory storage, and hence the virtual memory is no longer needed and can be dropped from future computers. Comment with reasons in favour of and against this thought.
  • 4.16 A two-level memory system has eight virtual pages on a disk to be mapped into four-page frames in the main memory. Assume the page frames are initially empty. During execution, a certain program generated the following page traced, 2, 0, 2,1, 7, 7, 6, 0,1, 2, 0, 3, 0, 4, 5,1, 5, 2,4, 5, 6, 7, 6, 2,4, 7, 3, 2,4, 4

a. Show the successive virtual pages residing in the four-page frames with respect to the above page trace using the circular FIFO page replacement policy. Compare the hit ratio in the main memory.

b. Repeat part(a) for the LRU page replacement policy. Compute the hit ratio in the main memory.

c. Compare the hit ratio in parts (a) and (b) and comment on the effectiveness of using the circular FIFO policy to approximate the LRU policy with respect to this particular page trace.

  • 4.17 "The page replacement policy to be adopted has a severe impact on the performance of the system." Discuss. What is the working set? How working set model affects the main memory hit ratio?
  • 4.18 What are the different page replacement policies that are commonly used? Write two page replacement policies that are used in a virtual memory system.

4.19 Consider a two-level memory, and M2. Let the hit ratio of M, be h. Let c, and c2 be the costs per kilobyte, st and s2 the memory capacities, and t, and t2 the access times, respectively.

a. Under what conditions will the average cost of the entire memory system approach c2?

b. What is the effective memory-access time ta of this hierarchy?

c. Let r = t2/t{ be the speed ratio of these two memories. Let £ = t1/ta be the access efficiency of the memory system. Express £ in terms of r and h.

d. What is the required hit ratio h to make E > 0.95 if r =100?

  • 4.20 Explain the need of auxiliary memory devices. How are the serial access memories organised? In what way are they different from main memory? Give the major differences being observed between tape drive and magnetic disk.
  • 4.21 Define the following for a disk system:

Ts = seek time;

R = rotation speed of the disk, in revolutions per second N = number of bits per sector C = capacity of a track, in bits

TA = time to access a sector; Build up a formula for TA as a function of these other parameters.

  • 4.22 A disk pack hasl5 surfaces. Storage area on each surface has an inner diameter of 20 cm and an outer diameter of 30cm. Maximum storage density on each track is
  • 2,000 bits/cm, and minimum spacing between the tracks is 0.25 mm. What would be the storage capacity of the pack? What would be the data-transfer rate in bytes/ sec at a rotational speed of 3,600 rpm?
  • 4.23 How long does it take to read a disk with 800 cylinders, each containing five tracks of 32 sectors each? First, all the sectors of track 0 are to be read starting at sector 0, then all the sectors of track 1 starting at sector 0, and so on. The rotation time is 20 ms, and a seek takeslO ms between adjacent cylinders and 50 ms for the worst case. Assume switching between tracks of a cylinder can be done instantaneously.
  • 4.24 Calculate how much disk space (in sectors, tracks, and surfaces) will be required to store 5,000 logical records, each is of 120byte, if the disk is a fixed sector of 512 bytes/sector, with 100 sectors per track, 120 tracks per surface, and 8 usable surfaces. Assume that records cannot span 2 sectors and ignore any file header records and track indexes, etc.
  • 4.25 Higher blocking factor allows more records to be accommodated in a tape reel and also takes lesser amount of time to process the tape, whereas using comparatively lower blocking factor, lesser number of records can be stored in the same tape with more time to process the tape. Explain why? In a practical situation, still we prefer reasonably lower blocking factor. Explain.
  • 4.26 What is the transfer rate of a 9-track magnetic tape unit whose tape speed is 120 inches per second and whose tape density is 1,600 linear bits per inch (bpi)?

4.27 A9-track magnetic tape reel of length 2,400 ft having a tape density of 1,600 linear bits per inch is rotating at a speed of 200 inches per second past the recording head. Data on tape are organised in physical records, where each physical record contains a fixed number of user-defined records call logical records. The inter record gap is 0.8 inch.

a. How long will it take to read a full tape of 240-byte logical records having a blocking factor 10 (each physical record contains 10 logical records)?

b. What will be the time taken if the blocking factor is 30?

c. How many logical records will the tape hold with each of the above blocking factors?

d. What is the effective over all transfer rate for each of the above two blocking factors?

e. What is the capacity of the tape?

4.28 From the manual, it is found that a commercial magneto-optical disk drive (CD-ROM) has the following specifications:

Formatted storage capacity of unit with 1,024-byte sectors 650 GB Formatted storage capacity of unit with 512-byte sectors 650 GB Read data-transfer rate with 1,024-byte sectors 0.87 MB/s

Read data-transfer rate with 512-byte sectors 0.79 MB/s

Write data-transfer rate with 1,024-byte sectors 0.29 MB/s

Write data-transfer rate with 512-byte sectors 0.26 MB/s

a. It is observed that larger (1,024 byte) sector provides greater storage capacity and higher data-transfer rates than the smaller (512 bytes) sector. Explain the reasons.

b. The larger sector size appears to have all the advantages, so why is the smaller size ever used?

c. Why does the writing operation take more time than reading?

  • 4.29 What are cache memories? Many computers use cache block size in the range of 32-128 bytes. What would be the major advantages and disadvantages being observed in making the size of cache blocks larger or smaller? Explain with the help of a neat sketch the operation of a cache indicating the write-back and write- through schemes.
  • 4.30 Compare the relative merits of the four cache memory organisations:

a. Fully associative cache

b. Direct-mapping cache

c. Set-associative cache

d. Sector-mapping cache

4.31 Discuss the advantages and disadvantages in using a common cache or separate caches for instructions and data. Explain the support from data paths, MMU and TLB, and memory bandwidth in the two cache architectures.

"Presence of multi-level caches in the memory organisation definitely enhances the performance." Define multi-level cache and justify the statement.

4.32 The cache design is associated with the following terms. Explain each one with relative merits and demerits, if appropriate:

a. Factors affecting cache hit ratios

b. Write-through versus write-back caches

c. Private cache versus shared cache

d. Cacheable versus non-cacheable data

e. Cache flushing policies

4.34 Consider a two-level memory hierarchy, a cache (M,) and memory (M2) with the following characteristics:

M,: 32K words, 50 ns access time M2:1M words, 400 ns access time

Assume eight-word cache blocks and a set size of 256 words with set-associative mapping.

a. Show the mapping between Mt and M2

b. Calculate the effective memory-access time with a cache hit ratio of h = 0.95.

4.35 The memory unit of a computer system is 128K x 16, and has a cache memory of 2K words. The cache memory uses direct mapping with a block size of four words.

a. How many bits are there in the tag, index, block, and word fields of the address format?

b. How many bits are there in each word of cache, and how are they divided into functions? Include a valid bit in the format.

c. How many blocks can the cache accommodate?

4.36 The access time of a cache memory is 90 ns and that of main memory is 900 ns. It is estimated that 80% of the memory requests are for read and the remaining 20% for write. The hit ratio for read accesses only is 0.9. A write-through procedure is used.

a. Considering only memory-read cycles, what is the average access time of the system?

b. When both read and write requests are considered, what would be the average access time of the system?

c. What is the hit ratio considering the write cycles also?

4.37 A hierarchical cache-main memory subsystem has the following specifications:

a. Cache access time is 50 ns.

b. Main memory access time is 550 ns.

c. 80% of memory requests are for read.

d. Hit ratio is 0.9 for read access.

e. Write-through scheme is employed.

Estimate:

a. average access time of the system considering only memory-read cycle.

b. average access time of the system both for read and write request.

4.38 A four-way set associative cache memory uses blocks of four words. The cache can accommodate a total of 2,048 words from the main memory. The main memory size is 256 x 32.

i. Construct the cache memory with all pertinent information needed to formulate it

ii. What is the size of the cache memory?

  • 4.39 What is cache miss? State and explain the different categories of cache miss. Explain the reasons behind such cache misses. Discuss three techniques to reduce the miss rate.
  • 4.40 What is meant by cache coherence problem? What are the reasons that create such problem? What are the different schemes being used to solve cache coherence problem?
  • 4.41 What is meant by interleaving of memory? What are the advantages that can be extracted from this arrangement? What is meant by degree of interleaving? Discuss briefly the different types of interleaving and their relative merits and drawbacks.
  • 4.42 Derive the logic of one cell of an associative memory. Where do you find the use of associative memory advantageous? Why are large associative memories rarely used?

Suggested References and Websites

Archibald, J. and Baer, J. L. "Cache coherence protocols: Evaluation using a multiprocessor simulation model." ACM Trans Prog Comput Syst, vol. 4, pp. 273-298, November 1986.

Crisp, R. "Direct RAMBUS Technology: The new main memory standard." IEEE Micro, November/ December 1997.

Hennessy, J. L. and Patterson, D. A. Computer Architecture: A Quantitative Approach. San Mateo, CA: Morgan Kaufmann, 1990.

Jacob, B., Ng, S. and Wang, D. Memory Systems: Cache, DRAM, Disk. Boston, MA: Morgan Kaufmann, 2008.

Przybylski, S. A. Cache and Memory Hierarchy Design, 2nd ed. San Mateo, CA: Morgan Kaufmann, 1990.

Smith, A. "Cache memories." ACM Computing Surveys, September 1992.

The RAM Guide: Provides an overview of RAM technology as well as a number of useful links.

Optical Storage Technology Association: Provides an abundant source of information about the technology used in optical storing, and vendors as well as extensive list of relevant links.

 
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