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Nanoprogramming

Nanoprogramming is a befitting approach in situations when many microinstructionsoccur several times in a microprogram. The concept of nanoprogramming was first introduced in the QM-1 computer designed sometimes in the 1970s by Nanodata Corporation.}}

FIGURE 6.11

CM models: (a) conventional microprogram - one level; (b) corresponding nanoprogram - two levels.

Subsequently, this approach has been successfully exploited in many areas, including in the versatile Motorola 68000 series of microprocessors.

Figure 6.11 illustrates the concept of nanoprogramming. Part (a) shows a microprogram having n microinstructions, each W bits wide. A total of nW bits of CM is needed to store this microprogram. Assume that a careful study of this microprogram revealed that only m different microinstructions were actually in heavy use, with m « n. A special m-word W-bit nano-memory could be used to store m such unique microinstructions. Each microinstruction in the original program in CM could then be replaced by the address of the nano-memory word containing the desired microinstruction. Since the nano-memory contains only m words, the CM in question will only need instructions, each being log2 m bits wide (the address of microinstruction held in nano-memory). This is illustrated in part (b) of the figure. Each microinstruction held in nano-memory is wide and allows for parallel operations within the logic unit. Thus, the use of CM is analogous to vertical microprogramming, since a relatively large number of small instructions are involved. The use of nano-memory, on the other hand, is analogous to horizontal microprogramming providing needed parallel operations.

The microprogram is executed as follows. The desired word is first fetched from the CM and is then placed in the microinstruction register. It is then used to point to the targeted nano-memory word to get the required microinstruction, which is then fetched and placed in the nanoinstruction register. The bits of this register are then used to control the gates for one cycle. At the end of the cycle, the next word is fetched from CM and the process is repeated. This is illustrated in Figure 6.12.

The CM space is not wasted since only those microinstructions that require the use of nano-memory will be pointing to it. Moreover, if two microinstructions in CM require identical nano-memory instructions, then each microinstruction can point to the same nano-memory instruction.

The primary objective of this approach is to save costly CM space, but at the cost of considerable slower execution. A machine with this two-level CM arrangement will run slower than the original one because the fetch cycle will now require two memory references: one to the CM and one to the nano-memory. These two fetches can never be overlapped to reduce time consumption.

FIGURE 6.12

Two-level CM organisation for nanoprogramming.

Example

Suppose an original microprogram is of 4096 x 100 bits, but consists of only 128 different microinstructions. A nano-memory of 128 x 100 bits will be sufficient to hold all such microinstructions. The CM then becomes only of 4096 x 7 bits (128 = 27, 7 bits are required to uniquely define an address in nano-memory), and each word in CM will be pointing to a nanoinstruction. Hence,

Without using nanoprogramming, the required CM size is:

Using nanoprogramming, the total amount of CM size is

Thus, the memory saving in this example is:

Optimization in nanoprogramming, however, could further be made possible. Recall that nanoprogramming is best suited and is found to be most effective when the same microinstructions are heavily used. If two microinstructions that were not really the same but appear to be almost the same could be treated as being the same, then the microprogram would contain fewer distinct microinstructions, each with a higher frequency of usage. Optimization is now carried out with a slight variation from the basic idea. Words in the nano-memory may be parameterized. For example, assume that two microinstructions may differ only in the field indicating which register is to be gated onto some bus.

By putting the register number in the CM instead of in the nano-memory (the register field in the nanoinstruction contains zero), the two microinstructions can both point to the same word in nano-memory. When the word is fetched and put into the microinstruction register, the register field is taken from the CM instead of nano-memory. Obviously, this type of operation demands special hardware, which is again not very complex to realize. But this approach, in turn, will definitely increase the width of the CM, and hence, it is difficult to decide whether it is a profitable proposition or not. The type of microinstruction set in use, however, will have the last word in this context.

 
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