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AES Datapaths on FPGAs: A State of the Art Analysis

Joao Carlos Resende and Ricardo Chaves

Introduction

The Advanced Encryption Standard (AES) has been the preferred block cipher algorithm for data security since its 2001 approval by the North American National Institute of Standards and Technology (NIST) [19]. In the field of Field-Programmable Gate Arrays (FPGA) technology, prototyping, easy-deployment, and experimentation has become less time consuming, increasing the amount of available options for a custom-made AES implementation. Options in the chosen datapath width, SBox implementation, round (un)rolling, pipelining, etc., result in different trade-offs in terms of throughput, resource usage, and overall efficiency. The main goal for this chapter is to provide the reader with an overall review of the updated state of the art techniques and architectures for AES implementations on FPGA.

This chapter is organized as follows: Sect. 1.2 provides an introduction to the AES algorithm. Section 1.3 insights the most common solutions for the implementation of each AES operation on FPGAs, while Sect.1.4 explores some architectural choices when implementing the complete AES cipher. Section 1.5 presents a performance comparison of the most updated state of the art, and Sect.1.6 concludes with some final remarks.

J.C. Resende • R. Chaves (B)

Instituto Superior Tecnico, Universidade de Lisboa/INESC-ID, Rua Alves Redol 9, 1000-029 Lisbon, Portugal e-mail: This email address is being protected from spam bots, you need Javascript enabled to view it

J.C. Resende

e-mail: This email address is being protected from spam bots, you need Javascript enabled to view it

© Springer International Publishing Switzerland 2017 N. Sklavos et al. (eds.), Hardware Security and Trust, DOI 10.1007/978-3-319-44318-8_1

 
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