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Scan Design: Basics, Advancements, and Vulnerabilities

Samah Mohamed Saeed, Sk Subidh Ali and Ozgur Sinanoglu

Introduction

Security of Integrated Circuits (IC) is a major concern. Cryptochips, which apply encryption and decryption algorithms, are used in many applications such as cell phones, computers, avionics, smart cards, and medical applications to provide a secure environment. As any IC should be tested for defects, which are physical imperfection in the IC, to screened out defective chips, cryptochip can be hacked using the test features in the chip itself. Thus, cryptochip’s test infrastructure can be turned into a backdoor to leak secret information of the chip.

Manufacturing test process targets ensuring a high level of quality and reliability of the chips with a minimum test cost. Providing a high test quality and low test cost is a major challenge in the test process. Test patterns are applied to detect faults, which represent defects at an abstracted functional level as a result of defects. To maximize the fault coverage, and, thus, the test quality, a large number of test patterns can be applied to detect as much defects as possible resulting in a large test data volume and, and thus, a long test time. The limited bandwidth as well as number of channels, which is used to transfer test data between the tester and the chip, can further prolong the test time. Although increasing the number of test channels can reduce the test time, it incurs higher tester cost. The end result is a high test cost. These interrelated challenges need to be tackled to ensure low-cost high-quality test.

S.M. Saeed (B)

University of Washington, Tacoma, WA 98402, USA e-mail: This email address is being protected from spam bots, you need Javascript enabled to view it ; This email address is being protected from spam bots, you need Javascript enabled to view it

S.S. Ali • O. Sinanoglu

New York University, 129188 Abu Dhabi, UAE e-mail: This email address is being protected from spam bots, you need Javascript enabled to view it ; This email address is being protected from spam bots, you need Javascript enabled to view it

O. Sinanoglu e-mail: This email address is being protected from spam bots, you need Javascript enabled to view it

© Springer International Publishing Switzerland 2017 N. Sklavos et al. (eds.), Hardware Security and Trust, DOI 10.1007/978-3-319-44318-8_6

The semiconductor industry develops and adopts Design for Testability (DfT) techniques that modify the IC design, while maintaining its functionality. DfT techniques provide internal access to the chip, which includes controlling and observing the content of the storage elements to ensure a high quality. While DfT methods provide low-cost high-quality test, the IC is no longer secure against attackers that misuse the internal access to the IC to leak secret information from the chip. Throughout this chapter, we highlight the advanced DfT techniques for manufacturing test and shed light on the vulnerability of these techniques in security critical applications.

 
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