Desktop version

Home arrow Computer Science arrow Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment

Conclusion

We have shown the methods necessary to ensure homogeneous placement and routing of delay-based PUFs on Altera Cyclone FPGAs. Without these PUF uniqueness is not achievable. A complete description detailing all required steps has so far been missing in the literature. Furthermore, we have shown how the communication between the FPGA and a PC can be managed, enabling also novice readers to embark directly on their own PUF experiments.

Section11.5 included insights from the authors’ most recent research results. Future work will consist of developing and refining methods to cope for example with location based delay biases or with the biases induced by different non-PUF switching activity. The application of programmable delay lines [3] in this field is a very promising perspective.

References

  • 1. Bohm C, Hofer M, Pribyl W. A microcontroller SRAM-PUF. In: 2011 5th international conference on network and system security (NSS); 2011. p. 269-73. doi:10.1109/ICNSS.2011. 6060013.
  • 2. Bossuet L, Ngo XT, Cherif Z, Fischer V. A PUF based on a transient effect ring oscillator and insensitive to locking phenomenon. IEEE Trans Emer Top Comput. 2014;2(1):30-6. doi:10. 1109/TETC.2013.2287182.
  • 3. Chen YY, Huang JL, Kuo T. Implementation of programmable delay lines on off-the-shelf GPGAS. In: AUTOTESTCON, IEEE; 2013. p. 1-4. doi:10.1109/AUTEST.2013.6645040.
  • 4. Feiten L, Martin T, Sauer M, Becker B. Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases. In: IEEE European test symposium; 2015. doi:10.1109/ ETS.2015.7138749.
  • 5. Feiten L, Spilla A, Sauer M, Schubert T, Becker B. Implementation and analysis of ring oscillator PUFs on 60 nm Altera Cyclone FPGAs. Inf Secur J Glob Perspect. 2013;22(5- 6):265-73. doi:10.1080/19393555.2014.891281.
  • 6. Fournier J, Loubet-Moundi P. Memory address scrambling revealed using fault attacks. In: 2010 workshop on fault diagnosis and tolerance in cryptography (FDTC); 2010. p. 30-6. doi:10.1109/FDTC.2010.13.
  • 7. Guajardo J, Kumar SS, Schrijen GJ, Tuyls P. FPGA intrinsic PUFs and their use for IP protection. In: Proceedings of the 9th international workshop on cryptographic hardware and embedded systems. Springer; 2007. p. 63-80. doi:10.1007/978-3-540-74735-2_5.
  • 8. Kumar S, Guajardo J, Maes R, Schrijen GJ, Tuyls P. The butterfly PUF: protecting ip on every fpga. In: IEEE international workshop on hardware-oriented security and trust, 2008. HOST; 2008. p. 67-70. doi:10.1109/HST.2008.4559053.
  • 9. Lim D, Lee J, Gassend B, Suh G, van Dijk M, Devadas S. Extracting secret keys from integrated circuits. IEEE Trans Very Large Scale Integr VLSI Syst. 2005;13(10):1200-5. doi:10.1109/ TVLSI.2005.859470.
  • 10. Maiti A, Kim I, Schaumont P. A robust physical unclonable function with enhanced challenge- response set. IEEE Trans Inf Forensics Secur. 2012;7(1):333-45. doi:10.1109/TIFS.2011. 2165540.
  • 11. Maiti A, Schaumont P. Improving the quality of a physical unclonable function using configurable ring oscillators. In: International conference on field programmable logic and applications, 2009. FPL; 2009. p. 703-7. doi:10.1109/FPL.2009.5272361.
  • 12. Merli D, Schuster D, Stumpf F, Sigl G. Semi-invasive EM attack on FPGA RO PUFs and countermeasures. In: Proceedings of the workshop on embedded systems security, WESS ’11. ACM; 2011. p. 2:1-2:9. doi:10.1145/2072274.2072276.
  • 13. Merli D, Stumpf F, Eckert C. Improving the quality of ring oscillator PUFs on FPGAs. In: Proceedings of the 5th workshop on embedded systems security; 2010. p. 9:1-9:9. doi:10. 1145/1873548.1873557.
  • 14. Note JB, Rannaud E. From the bitstream to the netlist. In: Proceedings of the 16th Int’l ACM/SIGDA symposium on FPGAs, FPGA ’08. ACM; 2008. p. 264. doi:10.1145/1344671. 1344729.
  • 15. Ruhrmair U, Solter J, Sehnke F. On the foundations of physical unclonable functions; 2009. https://eprint.iacr.org/2009/277.pdf.
  • 16. Sklavos N. Securing communication devices via physical unclonable functions (PUFs). In: Reimer H, Pohlmann N, Schneider W, editors. ISSE 2013 securing electronic business processes. Fachmedien Wiesbaden: Springer; 2013. p. 253-61. doi:10.1007/978-3-658-03371- 2_22.
  • 17. Skorobogatov S. Flash memory ‘bumping’ attacks. In: Mangard S, Standaert FX, editors. Cryptographic hardware and embedded systems, CHES 2010. Lecture notes in computer science, vol. 6225. Berlin Heidelberg: Springer; 2010. p. 158-172. doi:10.1007/978-3-642-15031-9_ 11.
  • 18. Suh G, O’Donnell C, Devadas S. Aegis: a single-chip secure processor. IEEE Des Test Comput. 2007;24(6):570-80. doi:10.1109/MDT.2007.179.
  • 19. Suh GE, Devadas S. Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th annual design automation conference; 2007. p. 9-14. doi:10.1145/1278480.1278484.
  • 20. Yin CE, Qu G. Temperature-aware cooperative ring oscillator PUF. In: Proceedings of the 2009 IEEE international workshop on hardware-oriented security and trust; 2009. p. 36-42. doi:10. 1109/HST.2009.5225055.
  • 21. Yu H, Leong P, Hinkelmann H, Moller L, Glesner M, Zipf P. Towards a unique FPGA-based identification circuit using process variations. In: International conference on field programmable logic and applications, 2009. FPL; 2009. p. 397-402. doi:10.1109/FPL.2009.5272255.
  • 22. Yu MD, Devadas S. Secure and robust error correction for physical unclonable functions. IEEE Des Test Comput. 2010;27(1):48-65. doi:10.1109/MDT.2010.25.
  • 23. Zhang J, Lin Y, Lyu Y, Qu G. A PUF-FSM binding scheme for FPGA IP protection and pay- per-device licensing. IEEE Trans Inf Forensics Secur. 2015;10(6):1137-50. doi:10.1109/TIFS. 2015.2400413.
 
Source
< Prev   CONTENTS   Source   Next >