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Experimental Results

Process Flow and Run Sheets

As explained in the previous section, after assessing the feasibility of PFVDMOS and determining process parameters with simulators, actual device fabrication was carried out. Both PFVDMOS and conventional devices were fabricated on 20 дш thick, 7 x 1015 cm-3, n/n+ epi-wafer.

Edge termination scheme

Fig. 10.7. Edge termination scheme.

There are 11 masks in total used for the fabrication of PFVDMOS. These are listed below.

  • (1) Mask 1: Oxide isolation
  • (2) Mask 2: Trench termination
  • (3) Mask 3: P-poly trench
  • (4) Mask 4: Poly gate
  • (5) Mask 5: P-body
  • (6) Mask 6: N+ source
  • (7) Mask 7: P+ P-body contact
  • (8) Mask 8: Contact
  • (9) Mask 9: Metal 1
  • (10) Mask 10: Via
  • (11) Mask 11: Metal 2.

Variations were introduced to Masks 1 and 2 to take into account possible undercuts during trench-etching. Other variations were made to Masks 3,5,6, and 7 mainly to ensure proper source/N+ contact and also dielectric isolation between source metal and gate poly while ensuring maximum p-body spacing to reduce resistance contribution from the narrow neck region formed between

Partial mask layout showing the top view of PF-VDMOS structure

Fig. 10.8. Partial mask layout showing the top view of PF-VDMOS structure.

two p-body regions (Fig. 10.1). Sufficient splits always have to be designed so that despite process variations, some devices will work. Here, the most tricky step is of p-poly doping. Hence, some splits have to be designed with implant angle and dose, so that best charge balance can be found.

The layout of a PFVDMOS device is shown in Fig. 10.8.

The run sheet of the process looks very different from the regular process flow as it includes all cleaning/inspection steps. As a sample, a few entries in the run sheet for PFVDMOS are included in Table 10.2.

 
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